1. Field of the Invention
The present invention relates to a clock regenerator for generating a clock, and more specifically to a clock regenerator for regenerating a clock from an inputted digital signal.
2. Description of the Related Art
For digital apparatuses such as communication apparatuses for processing digital signals there are known those to regenerate a clock required for the apparatus itself using input data received from a destination instrument and a recording medium. Japanese Laid-open Patent Application No. Sho63-249976 discloses as a clock extraction circuit such an apparatus to generate a clock.
As illustrated in FIG. 26, the aforementioned clock extraction circuit includes a gate 501, a phase comparator 502, an adder 503, a loop filter 504, a voltage controlled oscillator (hereinafter simply referred to as VCO) 505, a frequency divider 506, and a frequency comparator 507. The gate 501 of the clock extraction circuit interrupts a digital signal (an input data) with a dropout signal. The phase comparator 502 generates an output in response to a difference between phase of the digital signal inputted through the gate 501 and phase of the clock.
In contrast, the frequency comparator 507 generates an output in response to a difference between frequency of a reference signal and frequency of the clock. The adder 503 adds an output from the phase comparator 502 and an output from the frequency comparator 507. The loop filter 504 has a flat frequency characteristic between frequency f511 and f512, as illustrated in FIG. 27A. The loop filter 504 generates voltage in response to an addition result from the adder 503, which is outputted to the VCO 505. The VCO 503 has a frequency characteristic illustrated in FIG. 27B. The VCO 503 generates a signal having a frequency in response to the voltage applied from the loop filter 504. The frequency divider 506divides frequency of the signal generated by the VCO 505 to form the aforementioned clock. The clock extraction circuit thus generates the aforementioned clock in response to the aforementioned digital signal.
The foregoing prior art technique disclosed in the aforementioned Publication however suffers from the following difficulties. The adder 503 of the aforementioned clock extraction circuit is constructed with an analog circuit, and hence bad nonlinearity of the adder 503 affects on the addition result. Hereby, the addition result in response to a phase difference outputted from the phase comparator 502 and a frequency difference outputted from the frequency comparator 507 is prevented from being outputted from the adder 503, so that a clock responsive to the aforementioned digital signal is not regenerated.
Further, since the adder 503 is an analog circuit, and hence there is caused a difficulty that the adder 503 is formed with variations in its operation upon its manufacture, so that the aforementioned clock extraction circuit with uniform performance is not ensured.
As means to correct such difficulties with the prior art, there are known clock regenerators disclosed in Japanese Laid-open Patent Application Nos. Hei10-163864, Hei04-215338, and Hei11-41222. Each device disclosed in the above Publications is adapted such that it not only ensures a recovery clock having frequency and phase accurately in synchronism with input data without synchronizing with incorrect frequency upon recovering a clock from random data, but also it can rapidly return to a state where correct frequency and phase are in synchronism with the input data even when the synchronization becomes out of phase and phase and frequency of the recovery clock due to VCO are displaced from the input data.
However, in a clock recovery circuit used for main communication for example , there is required a specification, called jitter tolerance, in which even when input data has jitter and its frequency component fluctuates, the circuit must sufficiently follow up the input data. When the input data has jitter and its frequency component fluctuates, the recovery clock follows up the input data by changing its frequency. This does not mean that synchronization is out of phase, but means that the frequency merely changes to inevitably follow up the input data The device is however adapted such that it judges whether or not the frequency synchronization is out of phase with a fixed frequency taken as a reference. There happens accordingly a difficulty that it is judged in the course of the follow-up of the operation for the fluctuation of the input data that the frequency synchronization is out of phase, which might cause the required jitter tolerance not to be satisfied.
In view of the above, it is an object of the present invention to provide a clock regenerator capable of regenerating an accurate clock while securely following an input digital signal even when the signal fluctuates.
According to a first aspect of the present invention, there is provided a clock regenerator comprising:
an oscillating section for outputting a clock signal with a frequency in response to an inputted first or second comparison signal;
a first generating section for comparing the frequency of an inputted reference signal with that of the clock signal, and generating the first comparison signal in response to the frequency difference between the frequency of the inputted reference signal and that of the clock signal;
a second generating section for comparing the phase of a digital input data with that of the clock signal, and generating the second comparison signal in response to the phase difference between the phase of the digital input data and that of the clock signal;
a first changeover section for selecting either the first comparison signal fed from the first generating section or the second comparison signal fed from the second generating section, and outputting a selected signal to the oscillating section; and
a controlling section for investigating whether or not a frequency difference between the frequency of the reference signal and that of the clock signal falls within a predetermined range, and controlling the first changeover section, when the frequency difference is outside the predetermined range, such that the first comparison signal generated by the first generating section is selected, while controlling the first changeover section, when the frequency difference falls within the predetermined range (different with the first predetermined range), such that the second comparison signal generated by the second generating section is selected.
According to a second aspect of the present invention, there is provided a clock regenerator comprising:
an oscillating section for outputting a clock signal with a frequency in response to an inputted first or second comparison signal;
a first generating section for comparing the frequency of an inputted reference signal with that of the clock signal, and generating the first comparison signal in response to the frequency difference between the frequency of the inputted reference signal and that of the clock signal;
a second generating section for comparing the phase of a digital input data with that of the clock signal, and generating the second comparison signal in response to the phase difference between the phase of the digital input data and that of the clock signal;
a first changeover section for selecting either the first comparison signal fed from the first generating section or the second comparison signal fed from the second generating section, and outputting a selected signal to the oscillating section; and
a controlling section for investigating whether or not a frequency difference between the frequency of the reference signal and that of the clock signal falls within a first or a second predetermined range, and controlling the first changeover section when the frequency difference is outside the first predetermined range such that the first comparison signal generated by the first generating section is selected, while controlling the first changeover section when the frequency difference falls within the second predetermined range such that the second comparison signal generated by the second generating section is selected.
In the foregoing first and second aspects, a preferable mode is one wherein said oscillating section includes a voltage generating circuit for generating control voltage based upon said inputted first or second comparison signal and a voltage controlled oscillator for generating and outputting a clock signal with a frequency in response to said control voltage applied from said voltage generating circuit.
Also, a preferable mode is one wherein said controlling section investigates, based upon a comparison result of said first generating section, whether or not said frequency difference between the frequency of said reference signal and that of said clock signal falls within a predetermined range.
In addition, a preferable mode is one that wherein further comprises:
a correcting section for generating a corrected reference signal by means of matching the phase of a predetermined reference signal with a predetermined frequency to the phase of said clock signal fed from said oscillating section;
a second changeover section for selecting either said corrected reference signal fed from said correcting section or said predetermined reference signal, and thus outputting a selected signal as said reference signal to said first generating section; and
said controlling section for controlling said second changeover section so as to select said predetermined reference signal when said frequency difference is out of said predetermined range, while controlling said second changeover section so as to select said corrected reference signal when said frequency difference falls within said predetermined range.
Further, a preferable mode is one wherein said first generating section compares the frequency of said clock signal obtained by dividing, using said frequency divider, the frequency of said clock signals fed from said oscillating section with that of said reference signal.
Furthermore, a preferable mode is one wherein said correcting section generates said corrected reference signal by means of matching the phase of said predetermined reference signal with said pre-determined frequency to the phase of said clock signal obtained by dividing, using said frequency divider, the frequency of said clock signals fed from said oscillating section.
According to a third aspect of the present invention, there is provided a clock regenerator comprising:
circuit section for generating a first comparison signal in response to the frequency difference between the frequency of an inputted reference signal and that of a clock signal so as to obtain said clock signal with the frequency in response to said first comparison signal, and thereafter generating a second comparison signal in response to the phase difference between a phase of digital input data and that of said clock signal so as to obtain said clock signal in response to said second comparison signal.
According to a fourth aspect of the present invention, there is provided a clock regenerator comprising:
circuit section for changing operation from clock synchronization due to frequency comparison to clock synchronization due to phase comparison when a frequency difference between the frequency of an inputted reference signal and that of a clock signal falls within a first predetermined range,
while changing operation from clock synchronization due to said phase comparison to clock synchronization due to said frequency comparison when said frequency difference between the frequency of said inputted reference signal and that of said clock signal is out of a second predetermined range including said first predetermined range.